1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device and a method of fabricating the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for reducing a step coverage between a cell part and a periphery circuit part for a higher integrated semiconductor memory device.
2. Discussion of the Related Art
A conventional semiconductor memory device and a method of fabricating the same will be explained with reference to the accompanying drawings.
FIGS. 1A to 1M are cross-sectional views showing a conventional method of fabricating the semiconductor memory device.
An n-type well and a p-type well are formed in a semiconductor substrate, as shown in FIG. 1A.
In FIG. 1B, an isolation layer 4 for isolating a cell part from a periphery circuit part and a device isolation layer 3 for isolating a cell from one another are formed on predetermined portions of the substrate where the n-type well and the p-type well have been formed.
Subsequently, as shown in FIG. 1C, an ion implantation process is performed into an active region defined by the device isolation layer 3 and the isolation layer 4, in order to adjust a threshold voltage. At this time, the type of transistor, such as an NMOS or a PMOS transistor, determines the types of ions to be implanted.
Next, as shown in FIG. 1D, a word-line of a memory device is formed in the cell part. At this time, a gate is formed in the cell part as well as in the periphery circuit part. The word-line includes a gate insulating layer 5, a polygate 6, and a cap oxide layer 7 on the substrate.
Thereafter, as shown in FIG. 1E, a buffer oxide layer 8 is formed on the substrate excluding the cell transistor. The buffer oxide layer 8 serves to relieve stress imposed over the substrate during the ion implantation process. With the gate serving as a mask, ions are implanted to form lightly-doped impurity diffusion regions 9 for a source and a drain.
Then, a sidewall oxide layer 10 is formed on both sides of the gates, as shown in FIG. 2F. With the sidewall oxide layer 10 and gate serving as masks, an ion implantation process is carried out to form heavily-doped impurity diffusion regions having a lightly doped drain (LDD) structure. A first insulating layer 11 is then formed on the entire surface of the substrate where the cell transistors have been formed. Subsequently, a second insulating layer 12 made of boron phosphorus silicate glass (BPSG) is formed on the first insulating layer 11. Next, the first and second insulating layers 11 and 12 are selectively removed to form a bit-line contact hole 13.
In FIG. 1G, a polysilicon layer 14 doped with n-type impurity ions and a tungsten silicide layer 15 are deposited to completely bury the bit-line contact hole 13 and then selectively patterned to form a bit-line.
Thereafter, as shown in FIG. 1H, a third insulating layer 16 made of oxide is formed on the entire surface including the bit-line. A fourth insulating layer 17 made of nitride is deposited on the third insulating layer 16. Thereafter, a fifth insulating layer 18 made of BPSG is formed on the fourth insulating layer 17. Then, a sixth insulating layer 19 of oxide is formed on the fifth insulating layer 18. The insulating layers 19, 18, 17, 16, 12, and 11 at the other side of the cell transistor are partially removed to form storage node contact holes 20. Subsequently, a nitride sidewall 21 is formed on side surface of each of the storage node contact holes 20.
Next, as shown in FIG. 1I, storage node electrodes 22 are formed to respectively contact the impurity diffusion regions exposed by the storage node contact holes 20 at the other side of the cell transistor, and then the fifth and sixth insulating layers 18 and 19 are removed with wet-etching. A high dielectric layer 23 is then formed on the entire surface including the storage node electrodes 22.
Thereafter, as shown in FIG. 1J, a plate electrode 24 is formed on the storage node electrode 22 where the high dielectric layer 23 has already been formed.
Then, as shown in FIG. 1K, a seventh insulating layer 25 of oxide is formed on the entire surface including the cell transistor and capacitor for multi-wirings. Aluminum and anti-reflection layers are formed on the seventh insulating layer 25 and then selectively etched to form lower wiring layers 26. At this time, transistors and wiring layers are also formed in the periphery circuit part.
Next, as shown in FIG. 1L, an interlayer insulating layer 27 is formed on the entire surface including the lower wiring layers 26, and then a spin on glass (SOG) layer 28 is coated on the interlayer insulating layer 27. The interlayer insulating layer 27 is then etched-back to improve the step coverage of the device. Subsequently, an eighth insulating layer 29 of oxide is formed on the SOG layer 28. An interlayer contact hole 30 is formed by removing the eighth insulating layer 29, the SOG layer 28 and the interlayer insulating layer 27 to expose the lower wiring layer 26 over the periphery circuit region.
In FIG. 1M, a plug layer 31 is formed in the interlayer contact hole 30 to improve the electrical characteristics of wirings. Then, an upper wiring layer 32 made of aluminum and anti-reflection layer is formed to contact the plug layer 31.
The above-mentioned method has been used for mass production of DRAM devices having a capacitor over bit-line (COB) structure. However, in the conventional method, defective devices are frequently produced due to electrical short circuit in metal wirings in realizing high integration and super micronization. In particular, the main cause of the short circuit is caused by the step coverage between a cell part where a cell array is constructed and a periphery circuit part where periphery circuits are formed in the device. The periphery circuits controls the input and output of data by applying signals to word-lines and data lines in the cell part. Since capacitors are formed to store data in the cell part, a step coverage is generated by forming the cell part and the periphery circuit part.
Accordingly, the conventional semiconductor memory device and the method of fabricating the same have the following problems.
Due to the step coverage between a cell part and a periphery circuit part, the short circuit in metal wirings is frequently occurred in the devices. Specifically, this result from the metal wirings of the cell part positioned higher than those of the periphery circuit part and insulating layers (the eighth insulating layer 29, the SOG layer 28, and the interlayer insulating layer 27) that are not precisely defined in a photolithography process. Moreover, the SOG layer exposed in a middle portion of an interlayer contact hole absorbs moisture into the interlayer contact hole and corrodes the plug layer. As a result, the electrical characteristics of the upper and lower wirings is deteriorated.